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1 www.semtech.com SC2596 low voltage integrated ddr termination regulator power management revision: july 18, 2007 typical application circuit the SC2596 is an integrated linear ddr termination device, which provides a complete solution for ddr termination regulator designs; while meeting the jedec requirements of sstl-2 and sstl-18 specifications for ddr-sdram termination. the SC2596 regulates up to +/- 2.5a for ddr-i and +/- 1.5a for ddr-ii application requirements. v tt is regulated to track the v ref voltage over the entire current range with shoot through protection. a v sense pin is incorporated to provide excellent load regulation, along with a buffered reference voltage for internal use. the SC2596 also features a disable function which is to tri-state the output during suspend to ram (str) states by pulling the en pin low. ? ddr-i and ddr-ii memory termination ? sstl-2 and sstl-3 termination ? hstl termination ? pc motherboards ? graphics boards ? disk drives ? cd-rom drives ? sourcing or sinking 2.5a for ddr-i ? sourcing or sinking 1.5a for ddr-ii ? av cc undervoltage lockout ? reference output ? minimum number of external components ? accurate internal voltage divider ? disable function, puts device into sleep mode ? thermal shutdown ? over current protection ? available in soic-8 edp package ? weee and rohs compliant description features applications SC2596 gnd en vsense vref vddq avcc pvcc vtt vref 0 en vtt avcc vddq
2 ? 200 7 semt ech cor p. www.semtech.com SC2596 preliminary power management rete m ara p rete m ara p rete m ara p rete m ara p rete m ara p lo b m y s lo b m y s lo b m y s lo b m y s lo b m y s s n oitid n o c ts e t s n oitid n o c ts e t s n oitid n o c ts e t s n oitid n o c ts e t s n oitid n o c ts e t ni m ni m ni m ni m ni m p yt p yt p yt p yt p yt xa m xa m xa m xa m xa m stin u stin u stin u stin u stin u e g atlo v ec n erefe r v f e r i t u o _ f e r a m 0 = q d d v 9 4.0 q d d v 5.0 q d d v 1 5.0 v v f e r ec n a d e p m itu ptu o z f e r v i f e r a u 0 3 + ot a u 0 3- = 0 3 2 n oitalu g e r tu ptu o tt v )1( v( tt v - f e r ) i t u o a 0 = i t u o a 5.1- = i t u o a 5.1 + = 5 2- 0 5 2 + v m tn erru c tn ecseiu q i q i d a o l a 0 = 0 0 4 0 0 7 a u v a c c dlo hserh t elb a n e 1.2 2.2 v ec n a d e p m itu p ni q d d v z q d d v 0 0 1 k n w o dtu h s nitn erru c tn ecseiu q i d s 0 = n e 0 5 1 0 5 2 a u tn erru c e g a k a e l nip n e i d s _ q 0 = n e 1 a u e g atlo v dlo hserh t n e h v l v 2 8.0 v nitn erru c e g a k a e l tt v n w o dtu h s i l_ tt v ,v 5 2.1 = tt v ,v 0 = d s 5 2 ta o c 6 a u rete m ara p rete m ara p rete m ara p rete m ara p rete m ara p lo b m y s lo b m y s lo b m y s lo b m y s lo b m y s m u m ix a m m u m ix a m m u m ix a m m u m ix a m m u m ix a m stin u stin u stin u stin u stin u d n g ot q d d v ,c c v a ,c c v p v c c 0.6 + ot 3.0- v e g n a r erutare p m et n oitc n uj m u m ixa m t j 5 2 1 + ot 0 4- o c e g n a r erutare p m et e g arots t g t s 0 5 1 + ot 5 6- o c s 0 4-0 1 erutare p m et w olfe r ri k a e p t g k p 0 6 2 o c )le d o m yd o b n a m u h( g nita r d s e d s e 2 v k unless otherwise specified: t j = -40 o c to +125 o c, av cc = pv cc = 2.5v, v ddq = 2.5v. electrical characteristics (ddr-i) absolute maximum ratings exceeding the specifications below may result in permanent damage to the device, or device malfunction. operation outside of the parameters specifiedin the electrical characteristics section is not implied.
3 ? 200 7 semt ech cor p. www.semtech.com power management SC2596 note: (1) regulation is measured by using a load current pulse. (pulse width less than 10ms, duty cycle less than 2%, t a = 25 o c) rete m ara p rete m ara p rete m ara p rete m ara p rete m ara p lo b m y s lo b m y s lo b m y s lo b m y s lo b m y s s n oitid n o c ts e t s n oitid n o c ts e t s n oitid n o c ts e t s n oitid n o c ts e t s n oitid n o c ts e t ni m ni m ni m ni m ni m p yt p yt p yt p yt p yt xa m xa m xa m xa m xa m stin u stin u stin u stin u stin u tn erru c e s n e s v i e s n e s 0 5 0 0 2 a n n w o dtu h s la m re h t t d s 0 6 1 o c siseretsy h n w o dtu h s la m re h t t s y h _ d s 0 1 o c electrical characteristics (ddr-i cont.) unless otherwise specified: t j = -40 o c to +125 o c, av cc = pv cc = 2.5v, v ddq = 2.5v. rete m ara p rete m ara p rete m ara p rete m ara p rete m ara p lo b m y s lo b m y s lo b m y s lo b m y s lo b m y s s n oitid n o c ts e t s n oitid n o c ts e t s n oitid n o c ts e t s n oitid n o c ts e t s n oitid n o c ts e t ni m ni m ni m ni m ni m p yt p yt p yt p yt p yt xa m xa m xa m xa m xa m stin u stin u stin u stin u stin u e g atlo v ec n erefe r v f e r i t u o _ f e r a m 0 = q d d v 9 4.0 q d d v 5.0 q d d v 1 5.0 v v f e r ec n a d e p m itu ptu o z f e r v i f e r a u 0 3 + ot a u 0 3- = 0 3 2 n oitalu g e r tu ptu o tt v )1( v( tt v - f e r ) i t u o a 0 = i t u o a 0.1- = i t u o a 0.1 + = 5 2- 0 5 2 + v m tn erru c tn ecseiu q i q i d a o l a 0 = 0 0 4 0 0 7 a u v a c c dlo hserh t elb a n e 1.2 2.2 v ec n a d e p m itu p ni q d d v z q d d v 0 0 1 k n w o dtu h s nitn erru c tn ecseiu q i d s 0 = n e 0 5 1 0 5 2 a u tn erru c e g a k a e l nip n e i d s _ q 0 = n e 5.0 a u e g atlo v dlo hserh t n e h v l v 2 8.0 v nitn erru c e g a k a e l tt v n w o dtu h s i l_ tt v ,v 9.0 = tt v ,v 0 = d s 5 2 ta o c 6 a u tn erru c e s n e s v i e s n e s 0 5 0 0 2 a n n w o dtu h s la m re h t t d s 0 6 1 o c siseretsy h n w o dtu h s la m re h t t s y h _ d s 0 1 o c unless otherwise specified: t j = -40 o c to +125 o c, av cc = 3.3v, pv cc = v ddq = 1.8v. note: (1) regulation is measured by using a load current pulse. (pulse width less than 10ms, duty cycle less than 2%, t a = 25 o c) electrical characteristics (ddr-ii)
4 ? 200 7 semt ech cor p. www.semtech.com SC2596 preliminary power management waveforms start up. shut down. shut down by en. t ransient with +/- 1a load start up by en. 1a load avcc pvcc vtt io avcc pvcc vtt io avcc pvcc//vddq vtt io avcc pvcc//vddq vtt io avcc vddq//pvcc vref vtt avcc vddq//pvcc vref vtt avcc vddq//pvcc vref vtt avcc vddq//pvcc vref vtt avcc pvcc en vtt avcc pvcc en vtt avcc pvcc en vtt avcc pvcc en vtt
5 ? 200 7 semt ech cor p. www.semtech.com power management SC2596 waveforms maximum sourcing current vs avcc. (vddq=1.8v, pvcc=2.5v) maximum sinking current vs avcc. (vddq=1.8v, pvcc=2.5v) maximum sinking current vs avcc. (vddq=1.8v, pvcc=1.8v) maximum sourcing current vs avcc. (vddq=1.8v, pvcc=1.8v) 2.0 2.5 3.0 3.5 4.0 2 2.5 3 3.5 4 4.5 5 5.5 avcc (v) output current (a) 2.0 2.5 3.0 3.5 4.0 2 2.5 3 3.5 4 4.5 5 5.5 avcc (v) output current (a) 1.0 1.5 2.0 2.5 3.0 2 2.5 3 3.5 4 4.5 5 5.5 avcc (v) output current (a) 2.0 2.5 3.0 3.5 4.0 2 2.5 3 3.5 4 4.5 5 5.5 avcc (v) output current (a)
6 ? 200 7 semt ech cor p. www.semtech.com SC2596 preliminary power management pin configuration ordering information re b m u n tra p re b m u n tra p re b m u n tra p re b m u n tra p re b m u n tra p e g a k c a p e g a k c a p e g a k c a p e g a k c a p e g a k c a p )3( )3( )3( )3( )3( t( e g n a r .p m e t t( e g n a r .p m e t t( e g n a r .p m e t t( e g n a r .p m e t t( e g n a r .p m e t aa a aa )) ) )) t r t e s 6 9 5 2 c s )1( p d e l 8-cio s 5 0 1 + ot 0 4- o c b v e 6 9 5 2 c s )2( dra o b n oita ulav e notes:(1)only available in tape and reel packaging. a reel contains 2500 devices for edp soic-8. (2) evb provided with edp soic-8 package.(3) lead free product. this product is fully weee and rohs compli- ant. 1 2 3 4 vtt gnd (soic-8l-edp) 5 6 7 8 pvcc en avcc vsense vddq vref 1 2 3 4 vtt gnd top view (soic-8l-edp) 5 6 7 8 pvcc en avcc vsense vddq vref 1 2 3 4 vtt gnd (soic-8l-edp) 5 6 7 8 pvcc en avcc vsense vddq vref 1 2 3 4 vtt gnd top view (soic-8l-edp) 5 6 7 8 pvcc en avcc vsense vddq vref
7 ? 200 7 semt ech cor p. www.semtech.com power management SC2596 # nip # nip # nip # nip # nip e m a n nip e m a n nip e m a n nip e m a n nip e m a n nip n oitc n u f nip n oitc n u f nip n oitc n u f nip n oitc n u f nip n oitc n u f nip 1 d n g .d n u org 2 n e .w olsi nip n e n e h w d elb asid si 6 9 5 2 c s .nip elb a n e 3 e s n e s v rotica p ac ci m are c f n 0 0 1 ot f n 0 1 a tce n n o c .nip kca b d e ef a si nip e s n e s v si nip e s n e s v ot esolc rotica p ac siht ecalp d n a d n u org ot nip siht n e e wte b .n oitid n oc tn eis n art g niru d n oitallicso diova ot d eriu q er 4 f e r v la nretni e htfo tu ptu o d ereffu b e ht se divorp hcih w ,nip tu ptu o n a si nip f e r v m orf d etce n n oc e b dlu o hs rotica p ac ci m arec f n 0 0 1 a .e g atlov ec n erefer .ecarttro hs htiw d n u org ot nip f e r v 5 q d d v ot e g atlov ec n ereferla nretni g nita erc rof nip tu p ni n a si nip q d d v e h t .re divid rotsiser la nretni n a ot d etce n n oc si e g atlov q d d v e h t .tt v etalu g er la nretni e ht ot d etce n n oc si)2 / q d d v(re divid rotsiserfo p atlartn ec e h t g nitrev ni-n o n e ht d n a nip f e r v ot d etce n n oc situ ptu o hcih w ,reffu b e g atlov p o ol kca b d e ef e ht hti w .e g atlov ec n erefer e ht sa reifilp m a rorre e htfo tu p ni siti .ylesicerp 2 / q d d v e ht kcart sya wla lliw e g atlov tu ptu o tt v e ht,d esolc e ht ottxe n d e d d a e b dlu o hs rotica p ac ci m arec f u 1 a ta ht d e d n e m m ocer .ytin u m m i esio n e ht esa erc ni ot d n u org ot nip q d d v 6 c c v a c c v a e h t .yrtiucric lortn oc la nretni e htfo lla ylp p us ot d es u si nip c c v a e h t ot)lacipyt v 1.2( e g atlov dlo hserht o l v u sti n a htreta erg e b ot sa h e g atlov n a htre w olsi e g atlov c c v a fi .n oitare p o la m ro n ni e b ot 6 9 5 2 c s e ht w olla ec n a d e p m i h gih ni e b dlu o hs nip tt v e ht,e g atlov dlo hserht o l v u e ht .s utats 7 c c v p d a ol s w ard nip tt v e ht ere h w m orf e g atlov liar e ht se divorp nip c c v p e h t ts u m e g atlov c c v p e h t .c c v p d n a c c v a n e e wte b n oitati m ila siere h t .tn erruc .n oitalu g er e g atlovtu ptu o tcerroc e ht erus n e ot e g atlov c c v a otla u q e ro ssele b e htre h gih .e g atlov c c v p n o tn e d n e p e d si ytilib a p ac tn erruc ecru os tt v e h t .tn erruc ecru os e htre h gih ,c c v p n o e g atlov 8 tt v tn erruc s u o u nitn oc ecru os d n a k nis n acti.6 9 5 2 c s fo tu ptu o e htsi nip tt v e h t dlu o hs e n o ta ht d e d n e m m ocer siti .n oitalu g er d a oltn ellecxe g nip e e k elih w ro rotica p ac ci m arec f u 1 a d n a rotica p ac r s e w ol f u 0 2 2 e n o tsa elta es u ,rotica p ac ci m arec f u 8.6 a d n a rotica p ac citylortcele r s e h gih f u 0 2 2 e n o e g atlov e ht g nic u d er d n u org ot e n alp pirts tt v e ht n o d ecalp era hcih w .n oitid n oc tn eis n art d a olre d n u e kips l a m r e h t d a p .saiv elpitlu m g nis u e n alp d n u org ot tce n n o c .seso pru p g nik nista e h rof d a p .ylla nretni d etce n n oc to n pin descriptions
8 ? 200 7 semt ech cor p. www.semtech.com SC2596 preliminary power management block diagram +- error am p. avcc gnd uvlo + thermal shutdown vddq vsense vtt anti- shoot- thru + driver circuit pvcc en vref + - v re f buffe r description description description description descriptionSC2596 is a low-voltage, low-dropout ddr termination regulator with separate power supply to support both ddr1 and ddr2 applications. a v cc and pv cc can be tied together for ddr1 and can also be separated forddr2. SC2596 regulat es v tt t o the v oltage of vref . v tt will sink or source upto 2.5a. internal shoot-through protec- tion ensure both top and bottom mosfet will not con-duct while maintaining fast source-to-sink load transient. thermal shut-down and internal current limit protect SC2596 from shorted load or over-heated vref buff vref buff vref buff vref buff vref buffvref is derived from vddq with an accurate divide by op-amps(vref buffer). it is capable to sink and source 30ua. it is used as the reference voltage to the error amp. a 100nf or higher capacitor is recommended for vref pin t o gr ound; t o enhance the noise immunity fr om board, an additional pull-down resistor (1m ) is recomanded as well from vref pin to ground. error amp error amp error amp error amp error amplow input offset op-amp for the main linear regulator. it contr ols the v tt output v oltage and which side of the mosfet to turn on (or turn off) to achieve zero shootthrough current. anti-shoot thought driver anti-shoot thought driver anti-shoot thought driver anti-shoot thought driver anti-shoot thought driverbuffer stage takes the error voltage to control mosfet. internal current limit is incorporated to protect from shorted load. thermal shutdown & uvlo thermal shutdown & uvlo thermal shutdown & uvlo thermal shutdown & uvlo thermal shutdown & uvlothe thermal shutdown block prevent the junction tem- perature e x ceed 1 65 o c. uvl o cir cuit t o ensure pr oper power is available for correct operation of the ic.
9 ? 2007 semtech corp. www.semtech.com power management SC2596 overview double data rate (ddr) sdram was defined by jedec 1997. its clock speed is the same as previous sdram but data transfer speed is twice than previous sdram. by now, the requirement voltage range is changed from 3.3v to 2.5v or 1.8v; the power dissipation is smaller than sdram. for above reasons, it is very popular and widely used in m/b, n/b, video-cards, cd rom drives, disk drives. regarding the ddr power management solution, there are two topologies can be selected for system designers. one is switching mode regulator that has bigger sink/ source current capability, but the cost is higher and needs more board space. another solution is linear mode regu- lator, which costs less, and needs less board space. for two dimm motherboards, system designers usually choose the linear mode regulator for ddr power man- agement solution. application information thermal shutdown the SC2596 has built-in thermal detected circuit to pre- vent this device from over temperature and damage. the SC2596 goes into shunt down mode when tem- perature is higher than 165 o c. the protection condition will release when the temperature of device drop down by 10 o c. avcc and pvcc avcc and pvcc are the input supply pins for the SC2596. avcc is supply voltage for all the internal control circuitry. the avcc voltage has to be greater than its uvlo thresh- old voltage (2.1v typical) to allow the SC2596 to be nor- mal operation. the pvcc pin provides the rail voltage from where the vtt pin draws load current. there is a limitation between avcc and pvcc. the pvcc voltage must be less or equal to avcc voltage to ensure the correct vtt output voltage regulation. vsense vsense pin is a feedback pin from vtt plane. vtt plane is always a narrow and long strip plane in most montherboard applications. this long strip plane will cause a large trace inductance and trace resistance. consider the load transient condition, a fast load cur- rent going through vtt strip plane will create a voltage spike on vtt plane and a dc voltage drop for load current. it is recommanded the vsense pin should be connected center of vtt plane to improve regulation and transient response. a longer trace of vsense may pick up noise and cause the error of load regulation. hence designer should avoid a longer trace between vsense to vtt plane. a 100nf ceramic capacitor close to vsense pin is required. vref vref pin is an output pin to provid internal reference voltage. system designer can use the voltage for northbridge chipset and memory. it is necessary to add a ceramic capacitor (100nf) from vref pin to ground with shortest trace. typical application circuits & waveforms four different application circuits are shown below in fig- ure 1, figure 2, figure 3 and figure 4. each circuit is designed for a specific condition. see note a. and b. below for recommended power up sequencing. application_1: standard sstl-2 application the avcc pin, pvcc pin and the v ddq pin can be tied together for sstl-2 application (figure 1). it only needs a 2.5v power rail for normal operation. system designer can save the pcb space and reduce the cost. figure 1: standard sstl-2 application. csense 10nf en 1.25v vddq cout 220uf 1.25v cin1 1uf SC2596 gnd 1 en 2 vsense 3 vref 4 vddq 5 avcc 6 pvcc 7 vtt 8 cin2 100uf vtt cref 100nf 2.5v vref 0
10 ? 2007 semtech corp. www.semtech.com SC2596 preliminary power management application information (cont.) application_2: lower power loss configuration for sstl-2 if power loss is a major concern, separating the pvcc form avcc and vddq will be a good choice (figure 2). the pvcc can operate at lower voltage (1.8v to 2.5v) if 2.5v voltage is applied on avcc and the vddq, the source current is lower due to the lower operating voltage ap- plied on the pvcc. figure 2: lower power loss for sstl-2(ddr-i). application_3: high source current configuration if there is a need for vtt to source more current, espe- cially for ddr-ii applications, the system designer can tie the avcc and pvcc to 3.3v while has the vddq tie to 1. 8v. this configuration can ensure more than 2a source and sink capability from the vtt rail. figure 4: high current set up for sstl-18(ddr-ii). notes: (a) the preferred configuration for ddr-i applications is to tie avcc and pvcc to vddq, which is typically 2.5v. (b) if avcc and pvcc rails are tied together, then the vddq cannot lead the avcc and pvcc. figure 3: lower power loss for sstl-18(ddr-ii). csense 10nf en vddq 0.9v 0.9v cout 220uf cin1 1uf SC2596 gnd 1 en 2 vsense 3 vref 4 vddq 5 avcc 6 pvcc 7 vtt 8 vtt cin2 100uf cref 100nf 1.8v vref 0 2.5v 1m csense 10nf en 0.9v vddq 0.9v cout 220uf cin1 1uf SC2596 gnd 1 en 2 vsense 3 vref 4 vddq 5 avcc 6 pvcc 7 vtt 8 vtt cin2 100uf cref 100nf vref 1.8v 0 3.3v vref cout 220uf csense 10nf 2.5v 1.25v vtt cin1 100uf en cref 100nf cin2 1uf 0 SC2596 gnd 1 en 2 vsense 3 vref 4 vddq 5 avcc 6 pvcc 7 vtt 8 1.25v vddq 2.5v pvcc 2.5v
11 ? 200 7 semt ech cor p. www.semtech.com power management SC2596 layout guidelines1) the edp so-8 package of SC2596 can improve the thermal impedance ( jc ) significantly. a suitable thermal pad should be add when pcb layout. some thermal viasare required to connect the thermal pad to the pcb ground layer. this will improve the thermal performance. please refer to the recommanded landing pattern. 2) t o increase the noise immunity , a ceramic capacit or of 100nf is required to decouple the v ref pin with the shortest connection trace.3) t o reduce the noise on in put po w er rail f or standar d ss tl -2 application, a 1 00 f lo w esr capacit or and a 1 f ceramic capacitor capacitor have to be used on the input power rail with shortest possible connection.4) v tt output copper plane should be as large as possible. a 4.7uf to 10 f capacitor have to be used to decouple the v tt pin. 5) the trace be tw een v sense pin and v tt rail should be as short as possible and put a 10nf ~100nf capacitorclose this vsense pin. application information (cont.)
12 ? 200 7 semt ech cor p. www.semtech.com SC2596 preliminary power management t ypical application cir cuit ddr -ii v tt solution bill of material fe r fe r fe r fe r fe r yt q yt q yt q yt q yt q e c n erefe r e c n erefe r e c n erefe r e c n erefe r e c n erefe r e ula v /re b m u n tra p e ula v /re b m u n tra p e ula v /re b m u n tra p e ula v /re b m u n tra p e ula v /re b m u n tra p rerutc afu n a m rerutc afu n a m rerutc afu n a m rerutc afu n a m rerutc afu n a m 1 1 1 c 3 0 6 0 ,ci m are c,r 5 x ,v 5 2 ,f n 0 0 1 o e g ay 2 1 2 c 3 0 6 0 ,ci m are c ,r 5 x ,v 6 1 ,f n 0 1 o e g ay 3 1 3 c 3 0 6 0 ,ci m are c ,r 5 x ,v 6 1 ,f u 1 o e g ay 4 1 6 c 6 0 2 1 ,ci m are c ,r 5 x ,v 6 1 ,f u 0 1 o e g ay 5 1 4 c m u ni m ula ,v 3.6 ,f u 0 0 1 o e g ay 6 1 5 c m u ni m ula ,v 3.6 ,f u 0 2 2 n ocyb u r 7 1 1 r m h o m 1 o e g ay 8 1 1 u 6 9 5 2 c s hcet m e s r1 1m c1 100nf u3 SC2596 gnd 1 en 2 vsense 3 vref 4 vddq 5 avcc 6 pvcc 7 vtt 8 vref 0 en c5 2 2 0 u f vtt c4 1 0 0 u f c3 1uf 0.9v vddq 3.3v 1.8v c2 10nf 0.9v
13 ? 2007 semtech corp. www.semtech.com power management SC2596 outline drawing - power soic-8l (edp) land pattern - power soic-8l (edp) y this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 1. reference ipc-sm-782a, rlp no. 300a. 2. inches dimensions z p y x dim c g millimeters e .201 5.10 x failure to do so may compromise the thermal and/or functional performance of the device. shall be connected to a system ground plane. thermal vias in the land pattern of the exposed pad 3. f e d solder mask thermal via ?0.36mm d.098 2.49 f.096 2.44 z (c) g (.205) (5.20) p 3.00 .118 1.27 .050 0.60 .024 2.20 .087 7.40 .291 e see detail detail a a .050 bsc .236 bsc 8 .010 .150 .189 .154 .193 .012 - 8 0.25 1.27 bsc 6.00 bsc 3.90 4.90 - .157 .197 3.80 4.80 .020 0.31 4.00 5.00 0.51 bxn 2x n/2 tips seating aaa c e/2 2x 12 n a d a1 e1 bbb c a-b d ccc c e/2 a2 (.041) .004 .008 - .028 - - - - 0 .016 .007 .049 .000 .053 8 0 0.20 0.10 - 8 0.40 0.17 1.25 0.00 .041 .010 .069 .065 .005 1.35 (1.05) 0.72 - 1.04 0.25 - - - 1.75 1.65 0.13 0.25 - .010 .020 0.50 - c l (l1) 01 0.25 gage plane h 3. dimensions "e1" and "d" do not include mold flash, protrusions or gate burrs. -b- controlling dimensions are in millimeters (angles in degrees). datums and to be determined at datum plane notes: 1. 2. -a- -h- side view a b c d e h plane f f exposed pad l1 n 01 bbb aaa ccc a b a2 a1 d e e1 l h e c dim min millimeters nom dimensions inches min max max nom f .086.090.0942.192.292.39 h 4. reference jedec std ms -012, variation ba. contact information semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805)498-2111 fax (805)498-3804

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